MIL-STD-1750A

Military Standard Sixteen-Bit Computer Instruction Set Architecture

Copyright © 1980, 1982 by USAF

This document is provided for use with XGC compilation systems targeted to the MIL-STD-1750A and specifies the 1750A instruction set and architecture.

The text of this document is based on MIL-STD-1750A, 2 Jul 1980, with updated Notice 1, 21 May 1982.

Table of Contents
About This Document
1. Reader's Comments
1. Scope and Purpose
1.1. Scope
1.2. Purpose
1.3. Applicability
1.4. Benefits
2. Referenced Documents
3. Definitions
4. General Requirements
4.1. Data Formats
4.1.1. Single Precision Fixed Point Data
4.1.2. Double Precision Fixed Point Data
4.1.3. Fixed Point Operands
4.1.4. Results on Fixed Point Overflow
4.1.5. Floating Point Data
4.1.6. Extended Precision Floating Point Data
4.1.7. Floating Point Operands
4.1.8. Truncation of Floating Point Results
4.1.9. Results of Division
4.2. Instruction Formats
4.2.1. Register-to-Register Format
4.2.2. Instruction Counter Relative Format
4.2.3. Base Relative Format
4.2.4. Base Relative Indexed Format
4.2.5. Long Instruction Format
4.2.6. Immediate Opcode Extension Format
4.2.7. Special Format
4.3. Addressing Modes
4.3.1. Register Direct (R)
4.3.2. Memory Direct (D)
4.3.3. Memory Direct-Indexed (DX)
4.3.4. Memory Indirect (I)
4.3.5. Memory Indirect with Pre-Indexing (IX)
4.3.6. Immediate Long (IM)
4.3.7. Immediate Short (IS)
4.3.8. Instruction Counter Relative (ICR)
4.3.9. Base Relative (B)
4.3.10. Base Relative-Indexed (BX)
4.3.11. Special (S)
4.4. Registers and Support Features
4.4.1. General Registers
4.4.2. Special Registers
4.4.3. Stack
4.4.4. Processor Initialization
4.4.5. Interval Timers (optional)
4.5. Memory
4.5.1. Memory Addressing
4.5.2. Expanded Memory Addressing (optional)
4.5.3. Memory Parity (optional)
4.5.4. Memory Block Protect (optional)
4.5.5. References to Unimplemented Memory
4.5.6. Start up ROM (optional)
4.5.7. Reserved Memory Locations
4.6. Interrupt Control
4.6.1. Interrupts
4.7. Input/Output
4.7.1. Input
4.7.2. Output
4.7.3. Input/Output Commands
4.7.4. Input/Output Command Partitioning
4.7.5. Input/Output Interrupts (optional)
4.7.6. Dedicated I/O Memory Locations
4.8. Instructions
4.8.1. Invalid Instructions
4.8.2. Mnemonic Conventions
4.8.3. Instruction Matrix
4.8.4. Instruction Set Notation
5. Detailed Requirements
5.1. Execute Input/Output
5.2. Vectored Input/Output
5.3. Set Bit
5.4. Reset Bit
5.5. Test Bit
5.6. Test and Set Bit
5.7. Set Variable Bit in Register
5.8. Reset Variable Bit in Register
5.9. Test Variable Bit in Register
5.10. Shift Left Logical
5.11. Shift Right Logical
5.12. Shift Right Arithmetic
5.13. Shift Left Cyclic
5.14. Double Shift Left Logical
5.15. Double Shift Right Logical
5.16. Double Shift Right Arithmetic
5.17. Double Shift Left Cyclic
5.18. Shift Logical, Count in Register
5.19. Shift Arithmetic, Count in Register
5.20. Shift Cyclic, Count in Register
5.21. Double Shift Logical, Count in Register
5.22. Double Shift Arithmetic, Count in Register
5.23. Double Shift Cyclic, Count in Register
5.24. Jump on Condition
5.25. Jump to Subroutine
5.26. Subtract One and Jump
5.27. Branch Unconditionally
5.28. Branch if Equal to (Zero)
5.29. Branch if Less Than (Zero)
5.30. Branch to Executive
5.31. Branch if Less Than or Equal to (Zero)
5.32. Branch if Greater Than (Zero)
5.33. Branch if Not Equal to (Zero)
5.34. Branch if Greater Than or Equal to (Zero)
5.35. Load Status
5.36. Stack IC and Jump to Subroutine
5.37. Unstack IC and Return from Subroutine
5.38. Single Precision Load
5.39. Double Precision Load
5.40. Load Multiple Registers
5.41. Extended Precision Floating Point Load
5.42. Load from Upper Byte
5.43. Load from Lower Byte
5.44. Pop Multiple Registers off the Stack
5.45. Single Precision Store
5.46. Store a Non-Negative Constant
5.47. Move Multiple Words, Memory-to-Memory
5.48. Double Precision Store
5.49. Store Register Through Mask
5.50. Store Multiple Registers
5.51. Extended Precision Floating Point Store
5.52. Store into Upper Byte
5.53. Store into Lower Byte
5.54. Push Multiple Registers onto the Stack
5.55. Single Precision Integer Add
5.56. Increment Memory by a Positive Integer
5.57. Single Precision Absolute Value of Register
5.58. Double Precision Absolute Value of Register
5.59. Double Precision Integer Add
5.60. Floating Point Add
5.61. Extended Precision Floating Point Add
5.62. Floating Point Absolute Value of Register
5.63. Single Precision Integer Subtract
5.64. Decrement Memory by a Positive Integer
5.65. Single Precision Negate Register
5.66. Double Precision Negate Register
5.67. Double Precision Integer Subtract
5.68. Floating Point Subtract
5.69. Extended Precision Floating Point Subtract
5.70. Floating Point Negate Register
5.71. Single Precision Integer Multiply with 16-Bit Product
5.72. Single Precision Integer Multiply with 32-Bit Product
5.73. Double Precision Integer Multiply
5.74. Floating Point Multiply
5.75. Extended Precision Floating Point Multiply
5.76. Single Precision Integer Divide with 16-Bit Dividend
5.77. Single Precision Integer Divide with 32-Bit Dividend
5.78. Double Precision Integer Divide
5.79. Floating Point Divide
5.80. Extended Precision Floating Point Divide
5.81. Inclusive Logical OR
5.82. Logical AND
5.83. Exclusive Logical OR
5.84. Logical NAND
5.85. Convert Floating Point to 16-Bit Integer
5.86. Convert 16-Bit Integer to Floating Point
5.87. Convert Extended Precision Floating Point to 32-Bit Integer
5.88. Convert 32-bit Integer to Extended Precision Floating Point
5.89. Exchange Bytes in Register
5.90. Exchange Words in Registers
5.91. Single Precision Compare
5.92. Compare Between Limits
5.93. Double Precision Compare
5.94. Floating Point Compare
5.95. Extended Precision Floating Point Compare
5.96. No Operation
5.97. Break Point
5.98. Built-In-Function
Index
List of Tables
I. Single Precision Fixed Point Numbers
II. Double Precision Fixed Point Numbers
III. 32-Bit Floating Point Numbers
IV. 48-Bit Extended Floating Point Numbers
V. Addressing Modes and Instruction Formats
VI. Processor Reset State
VII. AL Code to Access Key Mapping
VIII. Interrupt Definitions
IX. Input/Output Channel Groups
X. Operation Code Matrix (Left)
Xr. Operation Code Matrix (Right)
XI. Extended Operation Codes (Left)
XIr. Extended Operation Codes (Right)
XII. Mandatory XIO Command Fields and Mnemonics
XIII. Optional XIO Command Fields and Mnemonics
List of Figures
1. Expanded Memory Mapping Diagram
2. Interrupt System Flowchart
3. Interrupt Vectoring System
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