| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4
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R DSLL RB,N | 65 | N-1 | RB | 1 <= N <= 16
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Description. The concatenated contents of the Derived Address, DA, and DA+1 (i.e., the concatenated contents of RB and RB+1), are shifted left logically N positions. The shifted results are stored in RB and RB+1. The double left shift logical operation is as follows: zeros enter the least significant bit position of RB+1, bits shifted out of the sign bit position of RB+1 enter the least significant bit of RB and bits shifted out of the sign bit of RB are lost. The condition status, CS, is set based on the result in registers RB and RB+1.
Note: N-1 = 0 represents a shift of one position.
Note: N-1 = 15 represents a shift of sixteen positions.
RB, RB+1 Before Shift
0 RB 15 0 RB+1 15
----------------------------- -----------------------------
| sabc | defg | hijk | lmnp | | sqrs | tuvw | xyzz | zzzz |
| 1 | | | | | 2 | | | |
----------------------------- -----------------------------
RB, RB+1 After Shift (N=4)
0 RB 15 0 RB+1 15
----------------------------- -----------------------------
| defg | hijk | lmnp | sqrs | | tuvw | xyzz | zzzz | 0000 |
| | | | 2 | | | | | |
----------------------------- -----------------------------
Register Transfer Description.
(RB,RB+1) <-- (RB,RB+1) Shifted left logically by N positions;
(CS) <-- 0010 if (RB,RB+1) = 0;
(CS) <-- 0001 if (RB,RB+1) < 0;
(CS) <-- 0100 if (RB,RB+1) >= 0;
Registers Affected. RB, RB+1, CS