| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4
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R NEG RA,RB | B4 | RA | RB |
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Description. The negative (i.e., the 2's complement) of the Derived Address, DO (i.e., the contents of register RB), is stored into register RA. The condition status, CS, is set based on the result in register RA.
Note: The negative of zero is zero.
Note: The negative of a number with a 1 in the sign bit and all other bits zero is the same word, and causes fixed point overflow to occur.
Register Transfer Description.
(RA) <-- -DO;
PI4 <-- 1, exit, if DO = 8000
16;
(CS) <-- 0010 if (RA) = 0;
(CS) <-- 0001 if (RA) < 0;
(CS) <-- 0100 if (RA) >= 0;
Registers Affected. RA, CS, PI