MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture
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5.6. Test and Set Bit 


Addr
Mode  Mnemonic          Format/Opcode
                           8      4     4             16
D     TSB   N,ADDR      --------------------------------------
DX    TSB   N,ADDR,RX   |  59  |  N  |  RX  |  |     ADDR    |
                        --------------------------------------

Description. Bit number N (0 <= N <= 15) of the Derived Operand, DO, is tested and set to one. The CS is set according to the test.

Note: External memory accesses shall be inhibited until this instruction is complete.

Register Transfer Description.

(CS) <-- 0010  and (DON) <-- 1 if DO N  = 0 and 0 <= N <= 15;
(CS) <-- 0001  if (DON) = 1 and N = 0;
(CS) <-- 0100  if (DON) = 1 and 1 <= N <= 15;

Registers Affected. CS

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Test Bit Up Set Variable Bit in Register