| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4
----------------------
R XORR RA,RB | E5 | RA | RB |
----------------------
8 4 4 16
D XOR RA,ADDR --------------------------------------
DX XOR RA,ADDR,RX | E4 | RA | RX | | ADDR |
--------------------------------------
8 4 4 16
--------------------------------------
IM XORM RA,DATA | 4A | RA | 9 | | DATA |
--------------------------------------
Description. The Derived Operand, DO, is bit-by-bit exclusively ORed with the contents of RA. The result is stored in RA. The condition status, CS, is set based on the result in RA.
Register Transfer Description.
(RA) <-- (RA) XOR DO;
(CS) <-- 0010 if (RA) = 0;
(CS) <-- 0001 if (RA) < 0;
(CS) <-- 0100 if (RA) >= 0;
Registers Affected. RA, CS