| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4 16
D SOJ RA,LABEL --------------------------------------
DX SOJ RA,LABEL,RX | 73 | RA | RX | | LABEL |
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Description. The 16 bit contents of register RA are decremented by one. Then if the content of register RA is zero, the next sequential instruction is executed. If the content of register RA is non-zero, then a jump to the Derived Address, DA, occurs.
Note: If RA = RX, then the derived address, DA, is calculated before RA is decremented.
Register Transfer Description.
(RA) <-- (RA) - 1;
(IC) <-- DA if (RA) /= 0;
(CS) <-- 0010 if (RA) = 0;
(CS) <-- 0001 if (RA) < 0;
(CS) <-- 0100 if (RA) >= 0;
Registers Affected. RA, CS, IC (if the jump is executed)