| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4 16
D VIO RA,ADDR --------------------------------------
DX VIO RA,ADDR,RX | 49 | RA | RX | | ADDR |
--------------------------------------
Description. The vectored input/output instruction performs the I/O operation as specified by the input/output vector table starting at the derived address, DA, as shown below:
---------------------
DA | CMD |
---------------------
DA + 1 | Vector Select |
---------------------
DA + 2 | Data | } one data word for each bit
--------------------- set in the vector select
... | ... |
The input/output operation or device address is specified by the sum of the CMD and the product of the bit number of the bit set in the vector select times the contents of RA. This device address is then interpreted as specified by the XIO instruction (see Section 5.1) with the exception that I/O data is transfered to or from DA + 2 + i rather than RA (where i starts at zero and is incremented after each transfer). This is a privileged instruction. If an illegal XIO command is encountered as part of a VIO chain, the following actions occur:
The illegal I/O command bit of the fault register (FT5) is set to a one.
The VIO chain is terminated, and the illegal XIO is treated as a NOP. This termination shall not affect execution of preceding XIO commands which are part of the VIO chain being executed.
Register Transfer Description.
Step 1. n <-- 0 and i <-- 0;
Step 2. if [DA + 1]n = 1, then I/O command = [DA] + n x (RA);
Step 3. FT5 <-- 1, exit, if XIO = illegal command;
Step 4. if [DA + 1]n = 1, then I/O data = [DA + 2 + i];
Step 5. if [DA + 1]n = 1, then i <-- i + 1;
Step 6. n <-- n + 1, exit, if n = 16;
Step 7. go to step 2;
Registers Affected. None