5.3. Set Bit


Addr
Mode  Mnemonic          Format/Opcode
                           8      4     4
                        ---------------------
R     SBR   N,RB        |  51  |  N  |  RB  |
                        ---------------------
                           8      4     4            16
D     SB    N,ADDR      --------------------------------------
DX    SB    N,ADDR,RX   |  50  |  N  |  RX  |  |    ADDR     |
                        --------------------------------------
                           8      4     4            16
I     SBI   N,ADDR      --------------------------------------
IX    SBI   N,ADDR,RX   |  52  |  N  |  RX  |  |    ADDR     |
                        --------------------------------------

Description. Bit number N of the Derived Operand, DO, is set to one. The MSB is designated bit number zero and the LSB is designated bit number fifteen.

Register Transfer Description.

DON <-- 1;

Registers Affected. RB