| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
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The instruction set shall support a minimum of 16 registers (R0 through R15). The registers may be used as accumulators, index registers, base registers, temporary operand memory, and stack pointers with the following restrictions:
Only registers R1, R2, ..., R15 may be used as index registers (RX).
Only four registers, R12, R13, R14, and R15 may be used as base registers for instructions having the Base Relative address mode.
R15 is the implicit stack pointer for the Push and Pop Multiple instructions (Opcode 8F16 and 9F16).
The general registers are not in the logical memory address space.
Instructions having the Base Relative addressing mode have a single accumulator. The register pair (R0,R1) is the accumulator for double precision and floating point operations. Register R2 is the accumulator for single precision operations, except multiply and divide base relative also use R3.
The general registers shall functionally appear to be 16 bits in length. For instructions requiring a 32-bit operation, adjacent registers shall be concatenated to form effective 32-bit registers. Instructions requiring 48-bit operation shall concatenate three adjacent registers to form an effective 48-bit register.
When registers are concatenated, the register specified by the instruction shall represent the most significant word. The register set wraps around, that is, R15 concatenates with R0 for 32-bit operations and R15 concatenates with R0 and R1 for 48-bit operations.
The instructions shall make use of the following special registers: instruction counter, status word, fault register, interrupt mask, pending interrupt register, and input/output interrupt code registers.
A 16-bit register used for program sequencing. It allows instructions within a range of 65,536 words to be executed. It is external to the general registers. It is saved in memory when an interrupt is serviced.
The instruction set shall reference a 16-bit status word register whose state is defined by some prior event occurrence in the computer. The figure below indicates the format for the SW with the following paragraphs describing the meaning of the Condition Status (CS) field, reserved bits, the Processor State (PS) field, and the Address State (AS) field.
------------------------------------- | CS | Reserved | PS | AS | ------------------------------------- 0 3 4 7 8 11 12 15
A four-bit field (bits 0 through 3) of the status word shall be dedicated to instruction result (i.e., instruction status bits) and is defined as condition status (CS). Bits 0, 1, 2, and 3 shall be identified as C, P, Z, and N, respectively, and their meanings are given by the following register transfer description:
C = (CS)0 = 1 if result generates a carry from an addition or no borrow from a subtraction
P = (CS)1 = 1 if result is greater than (zero)
Z = (CS)2 = 1 if result is equal to (zero)
N = (CS)3 = 1 if result is less than (zero)
Bits 4 through 7 of the status word shall be reserved.
A four-bit field (bits 8 through 11) of the status word shall be dedicated to the processor state (PS) code. The code value defined by the PS shall be used for the following two functions:
For implementations which include the memory access lock feature of the expanded memory addressing option (see Section 4.5.2.2), PS shall define the memory access key code for all instructions and operand references to memory. References to memory during the interrupt recognition sequence for vector table pointer fetches and linkage/service parameter store/read references shall not use PS to define the memory access key code, but shall use an implied PS = 0 value.
PS shall determine the legal/illegal criteria for privileged instructions. When PS = 0 and a privileged instruction execution is attempted, the instruction shall be legal and shall be executed properly as defined. When PS /= 0 and a privileged instruction execution is attempted, the instruction shall be illegal, shall be aborted, and the privileged instruction fault bit in the fault register (FT10) shall be set to one.
A four-bit field (bits 12 through 15) of the status word shall be dedicated to the address state (AS) code. For implementations which do not include the expanded memory addressing option, an address state fault shall be generated for any operation which attempts to modify AS to a non-zero value. For implementations which include the expanded memory addressing option, AS shall define the group (pair) of page register sets to be used for all instruction and operand references to memory. References to memory during the interrupt recognition sequence for vector table pointer fetches and service parameter load references shall not use AS to define the operand page register set, but shall use an implied AS = 0 value. The linkage parameter store references shall use the AS field of the new status word. For partial implementations which include less than 16 groups of page register sets for the expanded memory addressing option (see Section 4.5.2.3), the address state fault bit in the fault register (FT11) shall be set to one if any operation attempts to establish an AS value that is not implemented.
The fault register is a 16-bit register used for indicating machine error conditions. The logical OR of the fault register bits is used to generate the machine error interrupt. The fault register shall be read and cleared by an XIO instruction. If a particular fault bit is not implemented, then the bit shall be set to zero. The fault bits shall be assigned as specified in the following:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ----------------------------------------------------------------- |Memory | Parity | I/O |Spa| Illegal |Res| BITE | |Protect| | | re| |rvd| | -----------------------------------------------------------------
The bits shall have the following meaning when set to one (1) :
CPU Memory Protection Fault. The CPU has encountered an access fault, write protect fault, or execute protect fault.
DMA Memory Protection Fault. A DMA device has encountered an access fault or a write protect fault.
Memory Parity Fault.
PIO Channel Parity Fault.
DMA Channel Parity Fault.
Illegal I/O Command Fault. An attempt has been made to execute an unimplemented or reserved I/O command.
PIO Transmission Fault. Other I/O error checking devices, if used, may be ORed into this bit to indicate an error.
Spare.
Illegal Address Fault. A memory location has been addressed which is not physically present.
Illegal Instruction Fault. An attempt has been made to execute a reserved code.
Privileged Instruction Fault. An attempt has been made to execute a privileged instruction with PS /= 0.
Address State Fault. An attempt has been made to establish an AS value for an unimplemented page register set.
Reserved.
Built-in Test Fault. Hardware built-in test equipment (BITE) error has been detected.
Spare BITE. These bits are for use by the designer for future defining (coding, etc.) the BITE error which is detected. This can be used with Bit 13 to give a more complete error description.
The interrupt mask register is software controlled and contains a mask bit for each of the system interrupts. The interrupt system is defined in Section 4.6.
The pending interrupt request register is software and hardware controlled and contains the pending interrupts that are attempting to vector the instruction counter. A pending interrupt is set by a system interrupt signal. The pending interrupt bit that generates the interrupt request is cleared by hardware action during the interrupt processing prior to initiating software at the address defined by the new IC value. The register may be set, cleared, and read by the I/O instructions.
The input/output interrupt code registers, if implemented, are used to indicate which channel generated the input/output interrupt. One register is assigned for each of the two input/output interrupts. Each register is set by hardware to reflect the address of the highest priority channel requesting that level of interrupt. The address shall be 0016 for channel number 0, 0F16 for channel number 15, 7F16 for channel number 127, etc. The IOICs shall not be altered once the interrupt sequence has commenced until they are read by an I/O instruction.
Up to 512 sixteen bit registers for optional expanded memory addressing.
The memory fault status register provides the page register selection designators associated with memory faults. The page register designators (below) captured by the MFSR are valid for the memory reference causing the fault. The faults setting bits 0, 1, 2, or 8 of the Fault Register (FT) shall cause MFSR to be set.
------------------------------------- | LPA | RESERVED |IO| AS | ------------------------------------- 0 3 4 10 11 12 15
Address of page register within the set.
Must not be used.
Instruction/operand page set selector (1 = instruction).
Address of selected group.
The instruction set shall support a stack mechanism. The operation of the stacking mechanism shall be such that the "last-in, first-out" concept is used for adding items to the stack and the Stack Pointer (SP) register always contains the memory address where the last item is stored on the stack. The stack provides for nested subroutine linkage using register 15. The stack shall also reside in a user defined memory area. Two instructions shall use register number 15 (R15) as the implied system stack pointer: Push Multiple registers, PSHM (see Section 5.54), and Pop Multiple registers, POPM (see Section 5.44). The stack expands linearly toward zero as items are added to it.
Two instructions, Stack IC and Jump to Subroutine, SJS (see Section 5.36), and Unstack IC and Return from Subroutine, URS (see Section 5.37), allow the programmer to specify any of the 16 general registers as the stack pointer. The memory block immediately preceding the stack area may be protected (by user using memory protect RAM), thus providing a means of knowing (memory protect interrupt) when the stack limit is exceeded. The stack shall be addressed by the Stack IC and Jump to Subroutine, Unstack IC and Return from Subroutine, Push Multiple, and Pop Multiple instructions.
Table VI defines the processor reset state:
Table VI. Processor Reset State
| Register/Device/Function | Condition After Reset |
|---|---|
| Instruction Counter | All zeros |
| Status Word | All zeros |
| Fault Register | All zeros |
| Pending Interrupt Register | All zeros |
| Interrupt Mask Register | All zeros |
| General Registers | Indeterminate |
| Interrupts | Disabled |
| Timers A & B | Started and all zeros [a] |
| Page Registers | Group 0 enabled [a] |
| Page Registers AL Field | All zeros [a] |
| Page Registers W Field | Zero [a] |
| Page Registers E Field | Zero [a] |
| Page Registers PPA Field | Exact logical to physical [a] |
| Memory Protect RAM | Disabled and all zeros [a][b] |
| Start Up ROM | Enabled [a] |
| DMA Enable | Disabled [a] |
| Input Discretes | Indeterminate [a] |
| Trigger Go Indicator | Started [a] |
| Discrete Outputs | All zeros [a] |
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Notes: a. If implemented (optional) b. Main Memory Globally Protected |
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Upon application of power, the processor shall enter the reset state, the normal power up discrete shall be set (if implemented), and execution shall begin.
If implemented, then two interval timers shall be provided in the computer and shall be referred to as Timer A and Timer B. Both timers can be loaded, stopped, started, and read with the commands described in the XIO paragraph (see Section 5.1). The two timers shall be 16-bit counters which operate as follows. Effectively, a one is automatically added to the least significant bit of the timer. Bit fifteen is the least significant bit and shall represent the specified increment value of that timer, i.e., either 10 or 100 microseconds. An interrupt request is generated when a timer increments from FFFF to 000016. After power up, if the timers are not loaded by software, then an interrupt request is generated after 65,536 counts. A sample of the 16-bit counting sequence (shown in hex) is 0000, 0001, ..., 7FFF, 8000, ..., FFFF, 0000, ...,. At system reset or power up, the timers are initialized in accordance with Section 4.4.4.1. The timers are halted when a breakpoint, BPT (see Section 5.97), instruction is executed and the console is connected.