| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4
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R DABS RA,RB | A5 | RA | RB |
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Description. If the sign bit of the double precision Derived Operand, DO (i.e., the sign bit of register (RB,RB+1)), is a one, its negative or 2's complement is stored into register RA and RA+1, such that register RA contains the MSH of the result. However, if the sign bit of DO is a zero, it is stored, unchanged, into RA and RA+1. The condition status, CS, is set based on the result in register RA and RA+1.
Note: RA may equal RB.
Note: The absolute value of a number with a 1 in the sign bit and all other bits zero is the same word, and causes fixed point overflow to occur.
Register Transfer Description.
(RA, RA+1) <-- |DO|;
PI4 <-- 1, exit, if DO = 8000 0000
16;
(CS) <-- 0001 if (RA,RA+1) = 8000 0000
16;
(CS) <-- 0010 if (RA,RA+1) = 0;
(CS) <-- 0100 if (RA,RA+1) >= 0;
Registers Affected. RA, RA+1, CS, PI