| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4
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S MOV RA,RB | 93 | RA | RB |
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Description. This instruction allows the memory-to-memory transfer of N words where N is an integer between zero and 216 - 1 and is represented by the contents of RA+1. The contents of RB are the address of the first word to be transferred and the contents of RA are the address of where the first word is to be transferred. After each word transfer, RA and RB are incremented, and RA+1 is decremented.
Note: Any pending interrupts are honored after each single word transfer is completed. The IC points to the current instruction location until the last transfer is completed.
Note: RA has a final value of the last stored address plus one; RA+1 has a final value of zero.
Note: RB has a final value equal to the address of the last word transferred plus one.
Register Transfer Description.
Step 1: [(RA)] <-- [(RB)] if (RA+1) >= 0; Go to Step 4 otherwise;
Step 2: (RA) <-- (RA)+1, (RB) <-- (RB)+1, (RA+1) <-- (RA+1)-1;
Step 3: REPEAT STEPS 1 and 2;
Step 4: Set IC to next instruction address;
Registers Affected. RA, RA+1, RB