5.48. Double Precision Store


Addr
Mode  Mnemonic          Format/Opcode
                           4     2     2        8       12<=BR<=15
                        ------------------------------ 
B     DSTB   BR,DSPL    |  0  |  3  |  BR'  |  DSPL  |  BR'=BR-12
                        ------------------------------  RA=R0
                           4     2     2      4   4     12<=BR<=15
                        ------------------------------ 
BX    DSTX   BR,RX      |  4  |  0  |  BR'  | 3 | RX |  BR'=BR-12
                        ------------------------------  RA=R0
                           8      4      4           16
D     DST    RA,ADDR    --------------------------------------
DX    DST    RA,ADDR,RX |  96  |  RA  |  RX  |  |    ADDR    |
                        --------------------------------------
                           8      4      4           16
I     DSTI   RA,ADDR    --------------------------------------
IX    DSTI   RA,ADDR,RX |  98  |  RA  |  RX  |  |    ADDR    |
                        --------------------------------------

Description. The contents of registers RA and RA+1 are stored at the Derived Address, DA, and DA+1, respectively.

Register Transfer Description.

[DA, DA+1] <-- (RA, RA+1);

Registers Affected. None