5.82. Logical AND


Addr
Mode  Mnemonic          Format/Opcode
                           8      4      4
                        ----------------------
R     ANDR   RA,RB      |  E3  |  RA  |  RB  |
                        ----------------------
                          4   2   2     8         12<=BR<=15
                        ----------------------  
B     ANDB   BR,DSPL    | 3 | 1 | BR' | DSPL |    BR'=BR-12
                        ----------------------    RA=R2
                          4   2   2     4   4     12<=BR<=15
                        ------------------------  
BX    ANDX   BR,RX      | 4 | 0 | BR' | E | RX |  BR'=BR-12
                        ------------------------  RA=R2
                           8      4      4           16
D     AND    RA,ADDR    --------------------------------------
DX    AND    RA,ADDR,RX |  E2  |  RA  |  RX  |  |    ADDR    |
                        --------------------------------------
                           8      4      4           16
                        --------------------------------------
IM    ANDM   RA,DATA    |  4A  |  RA  |  7   |  |    DATA    |
                        --------------------------------------

Description. The Derived Operand, DO, is bit-by-bit ANDed with the contents of register RA. The result is stored in register RA. The condition status, CS, is set based on the result in register RA.

Register Transfer Description.

(RA) <-- (RA) ^ DO;
(CS) <-- 0010  if (RA) = 0;
(CS) <-- 0001  if (RA) < 0;
(CS) <-- 0100  if (RA) >= 0;

Registers Affected. RA, CS