| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4
----------------------
R ORR RA,RB | E1 | RA | RB |
----------------------
4 2 2 8 12<=BR<=15
----------------------
B ORB BR,DSPL | 3 | 0 | BR' | DSPL | BR'=BR-12
---------------------- RA=R2
4 2 2 4 4 12<=BR<=15
------------------------
BX ORBX BR,RX | 4 | 0 | BR' | F | RX | BR'=BR-12
------------------------ RA=R2
8 4 4 16
D OR RA,ADDR --------------------------------------
DX OR RA,ADDR,RX | EO | RA | RX | | ADDR |
--------------------------------------
8 4 4 16
--------------------------------------
IM ORIM RA,DATA | 4A | RA | 8 | | DATA |
--------------------------------------
Description. The Derived Operand, DO, is bit-by-bit inclusively ORed with the contents of RA. The result is stored in register RA. The condition status, CS, is set based on the result in register RA.
Register Transfer Description.
(RA) <-- (RA) v DO;
(CS) <-- 0010 if (RA) = 0;
(CS) <-- 0001 if (RA) < 0;
(CS) <-- 0100 if (RA) >= 0;
Registers Affected. RA, CS