MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
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Addr Mode Mnemonic Format/Opcode 8 4 4 ---------------------- R DLR RA,RB | 87 | RA | RB | ---------------------- 4 2 2 8 12<=BR<=15 ------------------------------ B DLB BR,DSPL | 0 | 1 | BR' | DSPL | BR'=BR-12 ------------------------------ RA=R0 4 2 2 4 4 12<=BR<=15 ------------------------------ BX DLBX BR,RX | 4 | 0 | BR' | 1 | RX | BR'=BR-12 ------------------------------ RA=R0 8 4 4 16 D DL RA,ADDR -------------------------------------- DX DL RA,ADDR,RX | 86 | RA | RX | | ADDR | -------------------------------------- 8 4 4 16 I DLI RA,ADDR -------------------------------------- IX DLI RA,ADDR,RX | 88 | RA | RX | | ADDR | --------------------------------------
Description. The double precision Derived Operand, DO, is loaded into the register RA and RA+1 such that the MSH of DO is in RA. The Condition Status, CS, is set based on the result in RA and RA+1.
Register Transfer Description.
(RA,RA+1) <-- DO;
(CS) <-- 0010 if (RA,RA+1) = 0 (Double fixed point zero);
(CS) <-- 0001 if (RA,RA+1) < 0;
(CS) <-- 0100 if (RA,RA+1) >= 0;
Registers Affected. RA, RA+1, CS