5.84. Logical NAND


Addr
Mode  Mnemonic          Format/Opcode
                           8      4      4
                        ----------------------
R     NR   RA,RB        |  E7  |  RA  |  RB  |
                        ----------------------
                           8      4      4           16
D     N    RA,ADDR      --------------------------------------
DX    N    RA,ADDR,RX   |  E6  |  RA  |  RX  |  |    ADDR    |
                        --------------------------------------
                           8      4      4           16
                        --------------------------------------
IM    NIM  RA,DATA      |  4A  |  RA  |  B   |  |    DATA    |
                        --------------------------------------

Description. The Derived Operand, DO, is bit-by-bit logically NANDed with the contents of register RA. The result is stored in RA.

Note: The logical NOT of a register can be attained with a NR instruction with RA = RB.

Register Transfer Description.

(RA) <-- ~((RA) ^ DO);
(CS) <-- 0010  if (RA) = 0;
(CS) <-- 0001  if (RA) < 0;
(CS) <-- 0100  if (RA) >= 0;

Registers Affected. RA, CS