| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4
----------------------
R DMR RA,RB | C7 | RA | RB |
----------------------
8 4 4 16
D DM RA,ADDR --------------------------------------
DX DM RA,ADDR,RX | C6 | RA | RX | | ADDR |
--------------------------------------
Description. The double precision Derived Operand, DO, a 32-bit 2's complement number, is multiplied by the contents of registers RA and RA+1, a 32-bit 2's complement number, with the MSH in RA. The LSH of the product is retained in RA and RA+1 as a 32-bit, 2's complement number. The MSH is lost. The Condition Status, CS, is set based on the double precision result in registers RA and RA+1. A fixed point overflow occurs if (1) both operands are of the same sign and the MSH of the product is not zero, or the sign bit of the LSH is not zero, or (2) if the operands are of opposite sign and the MSH of the product is not FFFF FFFF16, or the sign bit of the LSH is not one. A fixed point overflow does not occur if either of the operands is zero.
Register Transfer Description.
(RQ,RQ+1,RQ+2,RQ+3) <-- (RA,RA+1)i1 x DO;
(RA,RA+1)2 <-- (RQ+2,RQ+3);
PI4 <-- 1, if {(RA0)
1 = DO and {(RQ,RQ+1) /= 0 or (RQ+2
0) = 1}} or
{(RA0)1 /= DO0 and {(RQ,RQ+1) /= FFFF FFFF
16 or (RQ+20) = 0} and
{(RA)1 /= 0 and DO /= 0}};
(CS) <-- 0010 if (RA,RA+1) = 0;
(CS) <-- 0001 if (RA,RA+1) < 0;
(CS) <-- 0100 if (RA,RA+1) >= 0;
Registers Affected. RA, RA+1, CS, PI