MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture
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4.8. Instructions

4.8.1. Invalid Instructions

Attempted execution of an instruction whose first 16 bits are not defined by this standard shall cause the invalid instruction bit in the fault register (FT9) to be set, generating a machine error interrupt. The Built-In-Function is an exception; implemented Built-In-Functions do not cause FT9 to be set or the machine error interrupt to be generated. All undefined bit patterns in the first 16 bits of an instruction are reserved.

4.8.2. Mnemonic Conventions

Each instruction has an associated mnemonic convention. In general, the operation is one or two letters, e.g., L for load, A for add, ST for store.

Floating point operations have a prefix of F, e.g., FL for floating load, FA for floating add.

Double precision operations have a prefix of D, e.g., DL for double load, DA for double add.

Extended precision floating point operations have a prefix of EF, e.g., EFA for extended precision floating point add.

Register-to-register operations have a suffix of R, e.g., AR for single precision add register-to-register, FAR for floating add register-to-register.

Indirect memory reference is indicated by a suffix I, e.g., LI for Load Indirect.

Immediate addressing, using the address field as an operand, is indicated by a suffix of IM, e.g., AIM for single precision add immediate. Use of indexing is specified in assembly language by the occurrence of the operational field after the address field, e.g., FA A2,ALPHA,A5: floating add to register A2 from memory location ALPHA indexed by register A5.

Table IX. Input/Output Channel Groups

Output Input Usage
00XX 80XX PIO
03XX 83XX PIO
04XX 84XX Spare
1FXX 9FXX Spare
20XX A0XX Processor & Auxiliary Register Control
21XX A1XX Reserved
2FXX AFXX Reserved
30XX B0XX Spare
3FXX BFXX Spare
40XX C0XX Processor & Auxiliary Register Control
41XX C1XX Reserved
4FXX CFXX Reserved
50XX D0XX Memory Protect RAM
51XX D1XX Memory Address Extension (page register commands)
52XX D2XX Memory Address Extension (page register commands)
53XX D3XX Spare
7FXX FFXX Spare

4.8.3. Instruction Matrix

Table X contains the order type matrix which relates each instruction operation code to an assigned symbol. The numbers shown across the top of the matrix are hexadecimal numbers which represent the higher order four bits of the operation code, and the hexadecimal numbers along the left side represent the lower order four bits of the operation code. Table XI contains the order types and assigned mnemonics for the extended Operation Code instructions.

4.8.4. Instruction Set Notation

The text and register transfer descriptions are intended to complement each other. Ambiguities or omissions in one are resolved by the other. The following definitions and special symbols are associated with the instruction descriptions.

CPU Registers  
R0, R1, ..., R15 The 16, 16-bit general registers
IC Instruction Counter
SW Status Word
CS Condition Status. A 4-bit quantity that is set according to the result of instruction executions.
LP Linkage Pointer
SP Stack Pointer; R15 for the Push and Pop Multiple instructions
SVP Service Pointer
MK Interrupt Mask Register
PI Pending Interrupt Register
RA, RB An unspecified general register
Addressing Modes  
R Register Direct
D, DX Memory Direct, Memory Direct-Indexed
I, IX Memory Indirect, Memory Indirect with Pre-Indexing
IM, IMX Immediate Long, Immediate Long with Indexing
ISP, ISN Immediate Short with Positive Operand, Immediate Short with Negative Operand
ICR IC-Relative
B, BX Base Relative, Base Relative with Indexing
S Special
Data Quantities  
MSH,LSH Most Significant Half, Least Significant Half
MSB,LSB Most Significant Bit, Least Significant Bit
S.P., D.P., Ft.P., E.F.P Abbreviation for "Single Precision," "Double Precision," "Floating Point," and "Extended Floating Point" operations respectively.
MO Floating Point Derived Operand mantissa (fractional part): DO0-23 (Ft.P), DO0-23 DO32-47 (E.F.P.)
EO Floating point 8-bit 2's complement Derived Operand characteristic (exponent): DO24-31
MA Floating point register accumulator mantissa (fractional part): (RA,RA+1)0-23 (Ft.P.), (RA,RA+1)0-23 (RA+2)32-47 (E.F.P.)
EA Floating point 8-bit 2's complement register accumulator characteristic (exponent): (RA,RA+1)24-31
RQ, MP, MQ An entity used for register level transfer description clarification. These registers are not part of the general register file.
Miscellaneous  
(X) Contents of Register X
(X,X+1) Contents of concatenated Registers X and X+1
[X] Contents of memory address X
[X,X+1] Contents of sequential memory locations X and X+1
OVM Mantissa (fractional part) overflow
Exit Indicates termination of present register transfer operation (except the setting of the CS bits)
DA Derived Address
DO Derived Operand
N,M,n An integer number
DSPL Displacement
Xn If X is a CPU register or a data quantity (see above), then n specifies a bit position in X. If X is not a CPU register or a data quantity, then the number X is to the base n. If X is a number and n=16, then X is a 2's complement hexadecimal number.
Xi If X is a CPU register or a memory address, then i specifies the state of X. This notation is used in the register transfer descriptions to refer to the contents of a CPU register or a memory address at different times (states) of the execution of the instruction. If X is not a CPU register or a memory address, then the number X is raised to the ith power.
Symbols  
<-- Unilateral transfer designator
<--> Bilateral transfer designator
: Comparison Designator
x Indicates a "don't care" bit when used in a binary number
> Greater than
< Less than
= Equals
>= Greater than or equal
<= Less than or equal
^ Logical AND
v Logical OR
xor Exclusive OR
~ Logical NOT
|| Absolute value

Table X. Operation Code Matrix (Left)

  Load Store Integer Arithmetic Floating Point Logic Compare Opcode Extensions Bit Shift Jump
  0 1 2 3 4 5 6 7
0 LB BR12 AB BR12 FAB BR12 ORB BR12 BRX BR12[a] SB SLL JC
1 LB BR13 AB BR13 FAB BR13 ORB BR13 BRX BR13[a] SBR SRL CR
2 LB BR14 AB BR14 FAB BR14 ORB BR14 BRX BR14[a] SBI SRA CISP
3 LB BR15 AB BR15 FAB BR15 ORB BR15 BRX BR15[a] RB SLC CISM
4 DLB BR12 SBB BR12 FSB BR12 ANDB BR12   RBR   CBL
5 DLB BR13 SBB BR13 FSB BR13 ANDB BR13   RBI DSLL  
6 DLB BR14 SBB BR14 FSB BR14 ANDB BR14   TB DSRL DC
7 DLB BR15 SBB BR15 FSB BR15 ANDB BR15   TBR DSRA DCR
8 STB BR12 MB BR12 FMB BR12 CB BR12 XIO[a][b] TBI DSLC FC
9 STB BR13 MB BR13 FMB BR13 CB BR13 VIO[a][b] TSB   FCR
A STB BR14 MB BR14 FMB BR14 CB BR14 IMML SVBR SLR EFC
B STB BR15 MB BR15 FMB BR15 CB BR15     SAR EFCR
C DSTB BR12 DB BR12 FDB BR12 FCB BR12   RVBR SCR LSTI[b]
D DSTB BR13 DB BR13 FDB BR13 FCB BR13     DSLR LST[b]
E DSTB BR14 DB BR14 FDB BR14 FCB BR14   TVBR DSAR SJS
F DSTB BR15 DB BR15 FDB BR15 FCB BR15 BIF[c]   DSCR URS
Notes:
a. These order types represent instructions which have "extended" operation codes and are fully described in the instruction specifications and in Table V.
b. Privileged instructions
c. User Defined Built-In Function Opcode.

Table Xr. Operation Code Matrix (Right)

  Load Store Add Sub Mult Divide Logical Compare
  8 9 A B C D E F
0 L ST A S MS DV OR C
1 LR STC AR SR MSR DVR ORR CR
2 LISP STCI AISP SISP MISP DISP AND CISP
3 LISN MOV INCM DECM MISN DISN ANDR CISM
4 LI STI ABS NEG M D XOR CBL
5 LIM   DABS DNEG MR DR XORR  
6 DL DST DA DS DM DD N DC
7 DLR SRM DAR DSR DMR DDR NR DCR
8 DLI DSTI FA FS FM FD FLX FC
9 LM STM FAR FSR FMR FDR FLT FCR
A EFL EFST EFA EFS EFM EFD EFLX EFC
B LUB STUB EFAR EFSR EFMR EFDR EFLT EFCR
C LLB SLTB FABS FNEG     XBR  
D LUBI SUBI         XWR  
E LLBI SLBI            
F POPM PSHM           NOP

Table XI. Extended Operation Codes (Left)

MSH[a] Format[b] 0 1 2 3 4 5 6 7
40 BRX BR12 LBX DLBX STBX DSTX ABX SBBX MBX DBX
41 BRX BR13 LBX DLBX STBX DSTX ABX SBBX MBX DBX
42 BRX BR14 LBX DLBX STBX DSTX ABX SBBX MBX DBX
43 BRX BR15 LBX DLBX STBX DSTX ABX SBBX MBX DBX
                   
4A IMM   AIM SIM MIM MSIM DIM DVIM ANDM
Notes:
a. Most Significant Half
b. Base Relative Indexed Format

Table XIr. Extended Operation Codes (Right)

MSH[a] Format[b] 8 9 A B C D E F
40 BRX BR12 FABX FSBX FMBX FDBX CBX FCBX ANDX ORBX
41 BRX BR13 FABX FSBX FMBX FDBX CBX FCBX ANDX ORBX
42 BRX BR14 FABX FSBX FMBX FDBX CBX FCBX ANDX ORBX
43 BRX BR15 FABX FSBX FMBX FDBX CBX FCBX ANDX ORBX
                   
4A IMM ORIM XORM CIM NIM        
Notes:
a. Most Significant Half
b. Base Relative Indexed Format
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