MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
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Addr Mode Mnemonic Format/Opcode 8 4 4 ---------------------- R XWR RA,RB | ED | RA | RB | ----------------------
Description. The contents of register RA are exchanged with the contents of register RB. The CS is set based on the result in register RA.
Register Transfer Description.
(RA) <-->= (RB);
(CS) <-- 0010 if (RA) = 0;
(CS) <-- 0001 if (RA) < 0;
(CS) <-- 0100 if (RA) >= 0;
Registers Affected. RA, RB, CS