| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4
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S XBR RA | EC | RA | 0 |
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Description. The upper byte of register RA is exchanged with the lower byte of register RA. The CS is set based on the result in register RA.
Register Transfer Description.
(RA)0-7 <-->= (RA)8-15;
(CS) <-- 0010 if (RA) = 0;
(CS) <-- 0001 if (RA) < 0;
(CS) <-- 0100 if (RA) >= 0;
Registers Affected. RA, CS