| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4
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R SAR RA,RB | 6B | RA | RB | |(RB)| <= 16
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Description. The contents of register RA are shifted arithmetically N positions, where N is the contents of register RB. If N is positive ((RB0) = 0), then the shift direction is left; if N is negative (2's complement notation, (RB0 ) = 1), then the shift direction is right. The condition status, CS, is set based on the result in RA.
Note: N = 0 represents a shift of zero positions.
Note: If |N| >= 16, the fixed point overflow occurs, no shifting takes place, and this instruction is treated as a NOP (see Section 5.96).
Note: The contents of RB remain unchanged, unless RA = RB; in this event, the contents are shifted N positions.
Note: (See "Description" of the arithmetic shift instruction SRA (see Section 5.12) for definition of the right shift operation. Left shift causes "zeros" to be shifted into low order position of result.)
Note: Fixed point overflow occurs if the sign bit changes during a left shift.
Register Transfer Description.
PI4 <-- 1, exit, if |N| >= 16;
(RA) <-- (RA) Shifted left arithmetically (RB) positions,
if 16 >== (RB) >= 0;
(RA) <-- (RA) Shifted right arithmetically -(RB) positions,
if 0 >= (RB) >== -16;
PI4 <-- 1, if (RA0) changes during the shift;
(CS) <-- 0010 if (RA) = 0;
(CS) <-- 0001 if (RA) < 0;
(CS) <-- 0100 if (RA) >= 0;
Registers Affected. RA, RB, CS, PI