MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
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Addr Mode Mnemonic Format/Opcode 8 4 4 ---------------------- R TVBR RA,RB | 5E | RA | RB | ----------------------
Description. Bit number N (0 <= N <= 15) of register RB is tested where the least significant four bits of the contents of register RA is N. The Condition Status, CS, is then set to indicate non-zero if bit number N of register RB is a one. Otherwise, CS is set to indicate zero.
Register Transfer Description.
N = (RA)12-15;
(CS) <-- 0010 if (RBN ) = 0 and 0 <= N <= 15;
(CS) <-- 0001 if (RBN) = 1 and N = 0;
(CS) <-- 0100 if (RBN) = 1 and 1 <= N <= 15;
Registers Affected. CS