MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
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Addr Mode Mnemonic Format/Opcode 8 4 4 ---------------------- R EFCR RA,RB | FB | RA | RB | ---------------------- 8 4 4 16 D EFC RA,ADDR -------------------------------------- DX EFC RA,ADDR,RX | FA | RA | RX | | ADDR | --------------------------------------
Description. The extended precision floating Derived Operand, DO, is compared to the contents of registers RA, RA+1, and RA+2 where RA contains the most significant 16-bits of the extended precision floating point word. The condition status, CS, is set based on whether the contents of RA, RA+1, and RA+2 are less than, equal to or greater than the DO. The contents of RA, RA+1, and RA+2 are unchanged.
Note: This instruction does not cause overflow to occur.
Register Transfer Description.
(RA, RA+1, RA+2) : DO;
(CS) <-- 0010 if (RA, RA+1, RA+2) = DO;
(CS) <-- 0001 if (RA, RA+1, RA+2) < DO;
(CS) <-- 0100 if (RA, RA+1, RA+2) >= DO;
Registers Affected. CS