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The MIL-STD-1750A is a 16-bit computer that can address up to 64K words of data and 64K words of instructions. Using the standard memory management unit, it can directly address up to 1M words of instructions and indirectly address 1M words of data.
The proposed 1750W has 32-bit registers and a 32-bit mode. In its start-up mode it runs exactly as a 1750A, except for one additional XIO command that switches it to 32-bit mode. In 32-bit mode the 1750W is still word-addressed and has a 16-bit data bus. The address bus is wider and can be as wide as 32 bits. More likely it will be 24 bits wide to allow up to 16M words of code and data.
The 1750W can address 4G words of instructions plus 4G words of data, and does not require a memory management unit.
So why not just use a 32-bit computer?
The 1750 is a simple design and is available as a space-qualified part. The 1750 is space-proven and generally considered to be a low risk choice. The extension to 32 bits will retain these benefits. In comparison, many 32-bit designs are quite complicated. For example, the SPARC has a complicated register cache that is arguably not necessary with a modern compilation system that employs a register allocator.
We are considering the details of how this 32-bit design would work, and what impact it would have on the compilers. There are several options.
If you are interested in a wider 1750, please let us know.