5.68. Floating Point Subtract

Addr
Mode  Mnemonic          Format/Opcode
                           8      4      4
                        ----------------------
R     FSR    RA,RB      |  B9  |  RA  |  RB  |
                        ----------------------
                          4   2   2     8          12<=BR<=15
                        ----------------------   
B     FSB    BR,DSPL    | 2 | 1 | BR' | DSPL |     BR'=BR-12
                        ----------------------     RA=R0
                          4   2   2     4   4      12<=BR<=15
                        ------------------------ 
BX    FSBX   BR,RX      | 4 | 0 | BR' | 9 | RX |   BR'=BR-12
                        ------------------------   RA=R0
                           8      4      4           16
D     FS     RA,ADDR    --------------------------------------
DX    FS     RA,ADDR,RX |  B8  |  RA  |  RX  |  |    ADDR    |
                        --------------------------------------

Description. The floating point Derived Operand, DO, is floating point subtracted from the contents of registers RA and RA+1. The result is stored in registers RA and RA+1. The process of this operation is as follows: the mantissa of the number with the smaller algebraic exponent is shifted right and the exponent incremented by one for each bit shifted until the exponents are equal. The mantissa of the DO is then subtracted from (RA,RA+1). If the difference overflows the 24-bit mantissa, then it is shifted right one position, the sign bit restored, and the exponent incremented by one. If the exponent exceeds 7F₁₆ as a result of this incrementation, overflow occurs and the operation is terminated. If the sum does not result in exponent overflow, the result is normalized. If during the normalization process the exponent is decremented below 80₁₆, then underflow occurs and a zero is inserted for the result.

Register Transfer Description.

n = EA - EO;
EA <-- E0, if MA = 0;
MO <-- MO Shifted Right Arithmetic n positions, if n > 0 and MA /= 0;
MA <-- MA Shifted Right Arithmetic -n positions, EA <-- EO, if n < 0 and MO /= 0;
MA <-- MA - MO;
MA <-- MA Shifted Right Arithmetic 1 position, MA ₀ <-- ~MA₀, EA <-- EA+1, if OVM = 1;
PI₃ <-- 1, EA <-- 7F ₁₆, MA <-- 7FFF FF₁₆, exit, if EA >= 7F ₁₆ and MA₀ = 0;
PI₃ <-- 1, EA <-- 7F ₁₆, MA <-- 8000 00₁₆, exit, if EA >= 7F ₁₆ and MA₀ = 1;
EA, MA <-- normalized EA, MA;
PI₆ <-- 1, EA <-- 0, MA <-- 0, if EA < 80 ₁₆;
(CS) <-- 0010  if (RA,RA+1) = 0;
(CS) <-- 0001  if (RA,RA+1) < 0;
(CS) <-- 0100  if (RA,RA+1) > 0;

Registers Affected. RA, RA+1, CS, PI