5.67. Double Precision Integer Subtract

Addr
Mode  Mnemonic          Format/Opcode
                           8      4      4
                        ----------------------
R     DSR   RA,RB       |  B7  |  RA  |  RB  |
                        ----------------------
                           8      4      4           16
D     DS    RA,ADDR     --------------------------------------
DX    DS    RA,ADDR,RX  |  B6  |  RA  |  RX  |  |    ADDR    |
                        --------------------------------------

Description. The double precision Derived Operand, DO, is subtracted from the contents of registers RA and RA+1. The results, a 2's complement 32-bit difference, is stored in registers RA and RA+1. The MSH is RA. The condition status (CS) is set based on the double precision results in RA and RA+1, and carry. A fixed point overflow occurs if both operands are of opposite sign and the derived operand is the same as the sign of the difference.

Register Transfer Description.

(RA,RA+1)² <-- (RA,RA+1)¹ - DO, i.e., (RA,RA+1) - DO means {(RA,RA+1) + ~DO} + 1;
PI₄ <-- 1, if (RA₀) ¹ /= DO₀ and (RA₀) ² = DO₀;
(CS) <-- 0010  if  carry = 0 and (RA,RA+1) = 0;
(CS) <-- 0001  if  carry = 0 and (RA,RA+1) < 0;
(CS) <-- 0100  if  carry = 0 and (RA,RA+1) > 0;
(CS) <-- 1010  if  carry = 1 and (RA,RA+1) = 0;
(CS) <-- 1001  if  carry = 1 and (RA,RA+1) < 0;
(CS) <-- 1100  if  carry = 1 and (RA,RA+1) > 0;

Registers Affected. RA, RA+1, CS, PI