5.69. Extended Precision Floating Point Subtract

Addr
Mode  Mnemonic          Format/Opcode
                           8      4      4
                        ----------------------
R     EFSR   RA,RB      |  BB  |  RA  |  RB  |
                        ----------------------
                           8      4      4           16
D     EFS    RA,ADDR    --------------------------------------
DX    EFS    RA,ADDR,RX |  BA  |  RA  |  RX  |  |    ADDR    |
                        --------------------------------------

Description. The extended precision floating point Derived Operand, DO, is extended floating point subtracted from the contents of registers RA, RA+1, and RA+2. The result is stored in registers RA, RA+1, and RA+2. The process of this operation is as follows: The mantissa of the number with the smaller algebraic exponent is shifted right and the exponent is incremented by one for each bit shifted. When the exponents are equal, the mantissas are subtracted. If the difference overflows the 39-bit mantissa, then the difference is shifted right one position, the sign bit restored, and the exponent is incremented. If the exponent exceeds 7F₁₆ as a result of this incrementation, overflow occurs and the operation is terminated. If the difference does not result in exponent overflow, the result is normalized. If during the normalization process the exponent is decremented below 80₁₆, then underflow occurs and a zero is inserted for the result.

Register Transfer Description.

n = EA - E0;
EA <-- E0, if MA = 0;
MO <-- MO Shifted Right Arithmetic n positions, if n > 0 and MA /= 0;
MA <-- MA Shifted Right Arithmetic -n positions, EA <-- E0, if n < 0 and MO /= 0;
MA <-- MA - MO;
MA <-- MA Shifted Right Arithmetic 1 position, MA ₀ <-- ~MA₀, EA <-- EA+1, if OVM = 1;
PI₃ <-- 1, EA <-- 7F ₁₆, MA <-- 7FFF FF FFFF ₁₆, exit, if EA >= 7F ₁₆ and MA₀ = 0;
PI₃ <-- 1, EA <-- 7F ₁₆, MA <-- 8000 00 0000 ₁₆, exit, if EA >= 7F ₁₆ and MA₀ = 1;
EA, MA <-- normalized EA, MA;
PI₆ <-- 1, EA <-- 0, MA <-- 0, if EA < 80 ₁₆;
(CS) <-- 0010  if (RA,RA+1,RA+2) = 0;
(CS) <-- 0001  if (RA,RA+1,RA+2) < 0;
(CS) <-- 0100  if (RA,RA+1,RA+2) > 0;

Registers Affected. RA, RA+1, RA+2, CS, PI