5.40. Load Multiple Registers

Addr
Mode  Mnemonic          Format/Opcode
                           8      4     4            16
D     LM   N,ADDR       -------------------------------------
DX    LM   N,ADDR,RX    |  89  |  N  |  RX  |  |    ADDR    |
                        -------------------------------------
                                   0 <= N <= 15

Description. The contents of the Derived Address, DA, are loaded into register R0, then the contents of the DA+1 are loaded into register R1, ..., finally, the contents of DA+N are loaded into RN. Effectively, this instruction allows the transfer of (N+1) words from memory to the register file.

Register Transfer Description.

(R0) <-- [DA];
(R1) <-- [DA + 1];
(R2) <-- [DA + 2];
(RN) <-- [DA + N];

Registers Affected. R0 through RN