5.41. Extended Precision Floating Point Load

Addr
Mode  Mnemonic          Format/Opcode
                           8      4      4             16
D     EFL   RA,ADDR     ----------------------------------------
DX    EFL   RA,ADDR,RX  |  8A  |  RA  |  RX  |  |     ADDR     |
                        ----------------------------------------

Description. The extended precision floating point Derived Operand, DO, is loaded into registers RA, RA+1, and RA+2 such that the most significant 16-bits of the word are loaded into register RA. The condition status, CS, is set based on the results in registers RA, RA+1, and RA+2.

Register Transfer Description.

(RA, RA+1, RA+2) <-- DO;
(CS) <-- 0010  if (RA, RA+1, RA+2) = 0;
(CS) <-- 0001  if (RA, RA+1, RA+2) < 0;
(CS) <-- 0100  if (RA, RA+1, RA+2) > 0;

Registers Affected. RA, RA+1, RA+2, CS