Chapter 30. Target Dependent Features

Table of Contents
30.1. MIL-STD-1750 Options
30.2. Floating Point
30.3. M1750 Machine Directives
30.4. Opcodes
30.5. ERC32 Options
30.6. Enforcing aligned data
30.7. Floating Point
30.8. ERC32 Machine Directives

This section describes features of the assembler that are specific to the target computer.

30.1. MIL-STD-1750 Options

The assembler can assemble code for several different members of the MIL-STD-1750 family. The default is to assemble code for the MIL-STD-1750A. The following options may be used to change the default. These options control which instructions and addressing modes are permitted. The members of the MIL-STD-1750 family are very similar. For detailed information about the differences, see the draft military standard MIL-STD-1750B, which covers both the 1750A and the 1750B, or see your 1750 vendor's literature.

-A1750a, -A1750A

Assemble for the 1750A with no expanded memory. (the default)

-A1750b, -A1750B

Assemble for the 1750B with all instruction options but no expanded memory.

-Ama31750, -AMA31750

Assemble for the GEC-Plessey MA31750 in 1750B mode.

-Ammu

Support expanded memory.

-Ano-mmu

Do not support expanded memory.

-Ab1

Permit 1750B optional mathematical instructions.

-Ab2

Permit 1750B optional long loads and stores.

-Ab3

Permit 1750B optional unsigned arithmetic, load, and store byte instructions.

-Ano-b1

Reject 1750B optional mathematical instructions.

-Ano-b2

Reject 1750B optional long loads and stores.

-Ano-b3

Reject 1750B optional unsigned arithmetic, load, and store byte instructions.