| MIL-STD-1750A: Standard sixteen-bit computer architecture | ||
|---|---|---|
| Prev | Chapter 5. Detailed Requirements | Next |
Addr
Mode Mnemonic Format/Opcode
8 4 4
----------------------
R EFIX RA,RB | EA | RA | RB |
----------------------
Description. The integer portion of the floating point Derived Operand, DO (i.e., the contents of registers RB, RB+1, and RB+2), is stored into register RA and RA+1. If the actual value of the DO floating point exponent is greater than 1F16, then RA and RA+1 remain unchanged and a fixed point overflow occurs. The condition status, CS, is set based on the result in RA and RA+1.
Note: The algorithm truncates toward zero.
Register Transfer Description.
PI4 <-- 1, exit, if EO >= 1F
16;
(RA,RA+1) <-- Integer portion of DO;
(CS) <-- 0010 if (RA,RA+1) = 0;
(CS) <-- 0001 if (RA,RA+1) < 0;
(CS) <-- 0100 if (RA,RA+1) > 0;
Registers Affected. RA, RA+1, CS, PI