5.79. Floating Point Divide

Addr
Mode  Mnemonic          Format/Opcode
                           8      4      4
                        ----------------------
R     FDR   RA,RB       |  D9  |  RA  |  RB  |
                        ----------------------
                          4   2   2     8         12<=BR<=15
                        ----------------------
B     FDB   BR,DSPL     | 2 | 3 | BR' | DSPL |    BR'=BR-12
                        ----------------------    RA=RO
                          4   2   2     4   4     12<=BR<=15
                        ------------------------
BX    FDBX  BR,RX       | 4 | 0 | BR' | B | RX |  BR'=BR-12
                        ------------------------  RA=RO
                           8      4      4           16
D     FD    RA,ADDR     --------------------------------------
DX    FD    RA,ADDR,RX  |  D8  |  RA  |  RX  |  |    ADDR    |
                        --------------------------------------

Description. The floating point number in registers RA and RA+1 is divided by the floating point Derived Operand, DO. The result is stored in register RA and RA+1. A floating point overflow occurs if the exponent result exceeds 7F₁₆ at any point in the calculation process. Underflow occurs if the exponent result is less than 80₁₆ at any point in the process. If underflow occurs, then the quotient is forced to zero. A divide by zero yields a floating point overflow.

Register Transfer Description.

n = EA - E0;
n <-- 0, if MA = 0
PI₃ <-- 1, EA <-- 7F ₁₆, MA <-- 7FFF FF₁₆, exit, if MA ₀ = MO₀ and {n >= 7F ₁₆ or DO = 0};
PI₃ <-- 1, EA <-- 7F ₁₆, MA <-- 8000 00₁₆, exit, if MA ₀ /= MO₀ and {n >= 7F ₁₆ or DO = 0};
PI₆ <-- 1, EA <-- 0, MA <-- 0, exit, if n < 80 ₁₆;
MQ <-- MA / MO;
MQ <-- MQ Shift Right Arithmetic 1 position, n <-- n + 1, if MQ >== 1.0;
                                                        
PI₃ <-- 1, EA <-- 7F ₁₆, MA <-- 7FFF FF₁₆, exit, if n >= 7F ₁₆ and MQ₀ = 0;
PI₃ <-- 1, EA <-- 7F ₁₆, MA <-- 8000 00₁₆, exit, if n >= 7F ₁₆ and MQ₀ = 1;
EA <-- n;
MA <-- MQ_0-23;
(CS) <-- 0010  if (RA,RA+1) = 0;
(CS) <-- 0001  if (RA,RA+1) < 0;
(CS) <-- 0100  if (RA,RA+1) > 0;

Registers Affected. RA, RA+1, CS, PI