| MIL-STD-1750A: Standard sixteen-bit computer architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4
----------------------
R MR RA,RB | C5 | RA | RB |
----------------------
4 2 2 8 12<=BR<=15
----------------------
B MB BR,DSPL | 1 | 2 | BR' | DSPL | BR'=BR-12
---------------------- RA=R2
4 2 2 4 4 12<=BR<=15
------------------------
BX MBX BR,RX | 4 | 0 | BR' | 6 | RX | BR'=BR-12
------------------------ RA=R2
8 4 4 16
D M RA,ADDR --------------------------------------
DX M RA,ADDR,RX | C4 | RA | RX | | ADDR |
--------------------------------------
8 4 4 16
--------------------------------------
IM MIM RA,DATA | 4A | RA | 3 | | DATA |
--------------------------------------
Description. The Derived Operand, DO, is multiplied by the contents of register RA. The result, a 32-bit, 2's complement integer, is stored in registers RA and RA+1 with the MSH of the product in register RA. The Condition Status, CS, is set based on the result in registers RA and RA+1.
SPECIAL CASE: DO = (RA) = 8000 (the largest negative number), then DO x (RA) = 4000 0000.
Register Transfer Description.
(RA,RA+1) <-- (RA) x DO;
(CS) <-- 0010 if (RA,RA+1) = 0;
(CS) <-- 0001 if (RA,RA+1) < 0;
(CS) <-- 0100 if (RA,RA+1) > 0;
Registers Affected. RA, RA+1, CS