| MIL-STD-1750A: Standard sixteen-bit computer architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4
----------------------
R SR RA,RB | B1 | RA | RB |
----------------------
4 2 2 8 12<=BR<=15
----------------------
B SBB BR,DSPL | 1 | 1 | BR' | DSPL | BR'=BR-12
---------------------- RA=R2
4 2 2 4 4 12<=BR<=15
------------------------
BX SBBX BR,RX | 4 | 0 | BR' | 5 | RX | BR'=BR-12
------------------------ RA=R2
8 4 4
-----------------------
ISP SISP RA,N | B2 | RA | N-1 | 1<=N<=16
-----------------------
8 4 4 16
D S RA,ADDR --------------------------------------
DX S RA,ADDR,RX | B0 | RA | RX | | ADDR |
--------------------------------------
8 4 4 16
--------------------------------------
IM SIM RA,DATA | 4A | RA | 2 | | ADDR |
--------------------------------------
Description. The Derived Operand (DO) is subtracted from the contents of the RA register. The result, a 2's complement difference, is stored in RA. The condition status (CS) is set based on the result in register RA and carry. A fixed point overflow occurs if both operands are of opposite signs and the derived operand is the same as the sign of the difference.
Register Transfer Description.
(RA)2 <-- (RA)1 - DO,
i.e., (RA) - DO means {(RA) + ~DO} + 1;
PI4 <-- 1, if (RA0)
1 /= DO0 and (RA0)
2 = DO0
(CS) <-- 0010 if carry = 0 and (RA) = 0;
(CS) <-- 0001 if carry = 0 and (RA) < 0;
(CS) <-- 0100 if carry = 0 and (RA) > 0;
(CS) <-- 1010 if carry = 1 and (RA) = 0;
(CS) <-- 1001 if carry = 1 and (RA) < 0;
(CS) <-- 1100 if carry = 1 and (RA) > 0;
Registers Affected. RA, CS, PI