5.60. Floating Point Add

Addr
Mode  Mnemonic          Format/Opcode
                           8      4      4
                        ----------------------
R     FAR   RA,RB       |  A9  |  RA  |  RB  |
                        ----------------------
                          4   2   2     8  
                        ----------------------     12<=BR<=15
B     FAB   BR,DSPL     | 2 | 0 | BR' | DSPL |     BR'=BR-12
                        ----------------------     RA=R0
                          4   2   2     4   4 
                        ------------------------   12<=BR<=15
BX    FABX  BR,RX       | 4 | 0 | BR' | 8 | RX |   BR'=BR-12
                        ------------------------   RA=R0
                           8      4      4           16
D     FA    RA,ADDR     --------------------------------------
DX    FA    RA,ADDR,RX  |  A8  |  RA  |  RX  |  |    ADDR    |
                        --------------------------------------

Description. The floating point Derived Operand, DO, is floating point added to the contents of registers RA and RA+1. The result is stored in registers RA and RA+1. The process of this operation is as follows: the mantissa of the number with the smaller algebraic exponent is shifted right and the exponent incremented by one for each bit shifted until the exponents are equal. The mantissas are then added. If the sum overflows the 24-bit mantissa, then the sum is shifted right one position, the sign bit restored, and the exponent incremented by one. If the exponent exceeds 7F₁₆ as a result of this incrementation, overflow occurs and the operation is terminated. If the sum does not result in exponent overflow, the result is normalized. If in the normalization process the exponent is decremented below 80₁₆, then underflow occurs and a zero is inserted for the result.

Register Transfer Description.

N = EA - E0;
EA <-- E0, if MA = 0;
MO <-- MO Shifted Right Arithmetic n positions, if n > 0 and MA /= 0;
MA <-- MA Shifted Right Arithmetic -n positions, EA <-- E0, if n < 0 and MO /= 0;
MA <-- MA + MO;
                                              
MA <-- MA Shifted Right Arithmetic 1 position, MA ₀ <-- ~MA₀, EA <-- EA+1, 
        if OVM = 1;
PI₃ <-- 1, EA <-- 7F ₁₆ , MA <-- 7FFF FF₁₆ , exit, if EA >= 7F ₁₆ and MA₀ = 0;
PI₃ <-- 1, EA <-- 7F ₁₆, MA <-- 8000 00₁₆, exit, if EA >= 7F ₁₆ and MA₀ = 1;
EA, MA <-- normalized EA, MA;
PI₆ <-- 1, EA <-- 0, MA <-- 0, if EA < 80 ₁₆;
(CS) <-- 0010  if (RA,RA+1) = 0;
(CS) <-- 0001  if (RA,RA+1) < 0;
(CS) <-- 0100  if (RA,RA+1) > 0;

Registers Affected. RA, RA+1, CS, PI