5.50. Store Multiple Registers

Addr
Mode  Mnemonic          Format/Opcode
                           8      4      4           16
D     STM  N,ADDR       --------------------------------------
DX    STM  N,ADDR,RX    |  99  |   N  |  RX  |  |    ADDR    |
                        --------------------------------------

Description. The contents of register R0 are stored into the Derived Address, DA; then the contents of R1 are stored into DA+1; ...; finally, the contents of RN are stored into DA+N where N is an integer, 0 <= N <= 15. Effectively, this instruction allows the transfer of (N+1) words from the register file to memory.

Register Transfer Description.

[DA] <-- (R0);
[DA+1] <-- (R1);
[DA+2] <-- (R2);
[DA+N] <-- (RN)  0 <= N <= 15;

Registers Affected. None