| MIL-STD-1750A: Standard sixteen-bit computer architecture | ||
|---|---|---|
| Prev | Chapter 5. Detailed Requirements | Next |
Addr
Mode Mnemonic Format/Opcode
8 4 4 16
D JS RA,LABEL --------------------------------------
DX JS RA,LABEL,RX | 72 | RA | RX | | LABEL |
--------------------------------------
Description. The value of the instruction counter (the address of the next sequential instruction) is stored into register RA. Then, the IC is set to the derived address, DA, thus effecting the jump. This sets up the return from subroutine to the address stored in the register RA, i.e., an indexed unconditional jump from location zero using RA as the index register shall transfer control to the instruction following the JS instruction.
Note: If RA = RX, then the derived address, DA, is calculated before the IC is stored in RA.
Register Transfer Description.
(RA) <-- (IC);
(IC) <-- DA;
Registers Affected. RA, IC