| MIL-STD-1750A: Standard sixteen-bit computer architecture | ||
|---|---|---|
| Prev | Chapter 5. Detailed Requirements | Next |
Addr
Mode Mnemonic Format/Opcode
8 4 4
----------------------
R SLR RA,RB | 6A | RA | RB | |(RB)| <= 16
----------------------
Description. The contents of register RA are shifted logically N positions, where N is the contents of register RB. If N is positive ((RB0)=0), then the shift direction is left; if N is negative (2's complement notation, (RB0)=1), then the shift direction is right. The condition status, CS, is set based on the result in RA.
Note: N = 0 represents a shift of zero positions.
Note: If |N| >= 16, the fixed point overflow occurs, no shifting takes place, and this instruction is treated as a NOP (see Section 5.96).
Note: The contents of RB remain unchanged, unless RA = RB; in this event the contents are shifted N positions.
Note: (See "Description" of the logical shift instructions, SLL and SRL (see Section 5.10) and Section 5.11), for the definition of shift operations.)
Register Transfer Description.
PI4 <-- 1, exit, if |N| >= 16
(RA) <-- (RA) Shifted left logically by (RB) positions,
if 0 < (RB) <= 16;
(RA) <-- (RA) Shifted right logically by -(RB) positions,
if 0 >= (RB) >== -16;
(CS) <-- 0010 if (RA) = 0;
(CS) <-- 0001 if (RA) < 0;
(CS) <-- 0100 if (RA) > 0;
Registers Affected. RA, RB, CS, PI