| MIL-STD-1750A: Standard sixteen-bit computer architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4
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R DSRL RB,N | 66 | N-1 | RB | 1 <= N <= 16
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Description. The concatenated contents of the Derived Address, DA, and DA+1 (i.e., the concatenated contents of RB and RB+1), are shifted right logically N positions. The shifted results are stored in RB and RB+1. The double logical right shift operation is as follows: zeros enter the sign bit position of RB, bits shifted out of the least significant bit position of RB enter the sign bit position of RB+1 and bits shifted out of the least significant bit position of RB+1 are lost. The condition status, CS, is set based on the result in register RB and RB+1.
Note: N-1 = 0 represents a shift of one position.
Note: N-1 = 15 represents a shift of sixteen positions.
RB, RB+1 Before Shift
0 RB 15 0 RB+1 15
----------------------------- -----------------------------
| sabc | defg | hijk | lmnp | | sqrs | tuvw | xyzz | zzzz |
| 1 | | | | | 2 | | | |
----------------------------- -----------------------------
RB, RB+1 After Shift (N=4)
0 RB 15 0 RB+1 15
----------------------------- -----------------------------
| 0000 | sabc | defg | hijk | | lmnp | sqrs | tuvw | xyzz |
| | 1 | | | | | 2 | | |
----------------------------- -----------------------------
Register Transfer Description.
(RB,RB+1) <-- (RB,RB+1) Shifted right logically by N positions;
(CS) <-- 0010 if (RB,RB+1) = 0;
(CS) <-- 0001 if (RB,RB+1) < 0;
(CS) <-- 0100 if (RB,RB+1) > 0;
Registers Affected. RB, RB+1, CS