2.10. Working with Temic Revisions CBA and CCA

Revisions CBA and CCA of the Temic ERC32 chip-set require the compiler and assembler to apply the workarounds suggested by Temic in their "design considerations" lists. By default, GCC-ERC32 Version 1.4 applies no workarounds and targets the TSC695E. You can select revision CBA instead using the compiler option -mcca (which may also be written -mcpu=cba). Also the start file art0.S will require configuration. See the file for further instructions.

The following example illustrates some of the workarounds applied for the revision CBA. Note that the assembler option -w may be used to warn about any changes to the generated code made by the assembler.

double x = 1.0;
double z;

void
foo (double y)
{
  z = x * x  + y * y;
}

This next listing shows part of the assembler listing for a regular SPARC V7. This was generated using the compiler option -mv7.

  19 0010 85A08942              fmuld   %f2,%f2,%f2
  20 0014 D03BA060              std     %o0,[%sp+96]
  21 0018 CD1BA060              ldd     [%sp+96],%f6
  22 001c 91A00026              fmovs   %f6,%f8
  23 0020 93A00027              fmovs   %f7,%f9
  24 0024 89A18948              fmuld   %f6,%f8,%f4
  25 0028 85A08844              faddd   %f2,%f4,%f2
  26 002c C538E000              std     %f2,[%g3+%lo(z)]

The following listing shows part of the assembler listing for a revision CBA chip-set, and includes the warning messages generated for the -w assembler option. Compare this with the previous listing, noting that the single-length floating load and store instructions are generated where the compiler would normally generated double-length loads and stores, and that NOP instructions have been inserted between adjacent floating point operations (FPops).

...
  20 0014 85A08942              fmuld   %f2,%f2,%f2
  21 0018 D03BA060              std     %o0,[%sp+96]
  22 001c CD03A060              ld      [%sp+96],%f6
  23 0020 CF03A064              ld      [%sp+100],%f7
  24 0024 91A00026              fmovs   %f6,%f8
  25 0028 01000000              fmovs   %f7,%f9
****  Warning:TSC692E Rev B workaround 3.7: Adjacent FPop instructions, NOP inserted
  25      93A00027 
  26 0030 01000000              fmuld   %f6,%f8,%f4
****  Warning:TSC692E Rev B workaround 3.7: Adjacent FPop instructions, NOP inserted
  26      89A18948 
  27 0038 01000000              faddd   %f2,%f4,%f2
****  Warning:TSC692E Rev B workaround 3.7: Adjacent FPop instructions, NOP inserted
  27      85A08844 
  28 0040 01000000              st      %f2,[%g3+%lo(z)]
****  Warning:TSC692E Rev B workaround 3.4: Adjacent FPop and STF instructions, NOP inserted
  28      C520E000 
  29 0048 C720E000              st      %f3,[%g3+%lo(z+4)]
...