The simulator includes command line switches that are common to all versions, and switches that are specific to the target Microprocessor.
Verbose Mode. In normal mode the simulator only generates information in the case of an error. In verbose mode, useful information is generated as the simulation proceeds.
When simulation terminates, generates a report that includes execution time, number of clock cycles, and so on.
When simulation terminates, generates a report that lists any conditional branch instructions that have not been executed both ways. You can use this option to identify blocks of code that have not been covered by a test case.
When simulation terminates, generates a report that lists any instructions that were not processed. You can use this option to identify blocks of code that are unreachable from the program entry point.
Trace mode. Use this option to get a continuous listing of instructions as they are processed. The listing includes the execution time so far, the program counter, the instruction processed. If you compiled with the debug option, then the listing will also include source file line numbers.
Delays the start of tracing by D microseconds. Use this option to skip unwanted lines of trace output.
Introduces further target-specific options: