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2.11. Working with Temic Revisions CBA and CCA

Revisions CBA and CCA of the Temic ERC32 chip-set require the compiler and assembler to apply the workarounds suggested by Temic in their "design considerations" lists. By default, ERC32 Ada Version 1.7 compiles for the single-chip TSC695E. You can apply the workarounds for the Temic revision CBA chip-set using the compile-time option -mcba. You can select revision CCA instead using the compiler option -mcca (which may also be written -mcpu=cca).

The following example illustrates some of the workarounds applied for the revision CBA. Note that the assembler option -w may be used to warn about any changes to the generated code made by the assembler.

Example 2-22. Program that Requires CBA Workarounds

package EG2 is
   x : Long_Float := 1.0;
   z : Long_Float;
   procedure Foo (y : Long_Float);
end EG2;

package body EG2 is
   procedure Foo (y : Long_Float) is
   begin
      z := x * x + y * y;
   end Foo;
end EG2;

This next listing shows part of the assembler listing for a regular SPARC V7. This was generated using the compiler option -mv7.

Example 2-23. SPARC V7 Generated Code

  17                    eg2__foo:
  18 0000 9C03BF90              add     %sp,-112,%sp
  19 0004 07000000              sethi   %hi(eg2__z),%g3
  20 0008 05000000              sethi   %hi(eg2__x),%g2
  21 000c C518A000              ldd     [%g2+%lo(eg2__x)],%f2
  22 0010 85A08942              fmuld   %f2,%f2,%f2
  23 0014 D03BA060              std     %o0,[%sp+96]
  24 0018 CD1BA060              ldd     [%sp+96],%f6
  25 001c 91A00026              fmovs   %f6,%f8
  26 0020 93A00027              fmovs   %f7,%f9
  27 0024 89A18948              fmuld   %f6,%f8,%f4
  28 0028 85A08844              faddd   %f2,%f4,%f2
  29 002c C538E000              std     %f2,[%g3+%lo(eg2__z)]
  30 0030 81C3E008              retl
  31 0034 9C23BF90              sub     %sp,-112,%sp

The following listing shows part of the assembler listing for a revision CBA chip-set, and includes the warning messages generated for the -w assembler option. Compare this with the previous listing, noting that the single-length floating load and store instructions are generated where the compiler would normally generated double-length loads and stores, and that NOP instructions have been inserted between adjacent floating point operations (FPops).

Example 2-24. Code Generated for Revision CBA

...
  17                    eg2__foo:
  18 0000 9C03BF90              add     %sp,-112,%sp
  19 0004 07000000              sethi   %hi(eg2__z),%g3
  20 0008 05000000              sethi   %hi(eg2__x),%g2
  21 000c C500A000              ld      [%g2+%lo(eg2__x)],%f2
  22 0010 C700A000              ld      [%g2+%lo(eg2__x+4)],%f3
  23 0014 85A08942              fmuld   %f2,%f2,%f2
  24 0018 D03BA060              std     %o0,[%sp+96]
  25 001c CD03A060              ld      [%sp+96],%f6
  26 0020 CF03A064              ld      [%sp+100],%f7
  27 0024 91A00026              fmovs   %f6,%f8
  28 0028 01000000              fmovs   %f7,%f9
****  Warning:TSC692E Rev B workaround 3.7: Adjacent FPop instructions, NOP inserted
  28      93A00027
  29 0030 01000000              fmuld   %f6,%f8,%f4
****  Warning:TSC692E Rev B workaround 3.7: Adjacent FPop instructions, NOP inserted
  29      89A18948
  30 0038 01000000              faddd   %f2,%f4,%f2
****  Warning:TSC692E Rev B workaround 3.7: Adjacent FPop instructions, NOP inserted
  30      85A08844
  31 0040 01000000              st      %f2,[%g3+%lo(eg2__z)]
****  Warning:TSC692E Rev B workaround 3.4: Adjacent FPop and STF, NOP inserted
  31      C520E000
  32 0048 C720E000              st      %f3,[%g3+%lo(eg2__z+4)]
  33 004c 81C3E008              retl
  34 0050 9C23BF90              sub     %sp,-112,%sp
...
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